1. Field of the Invention
This invention relates to a drive circuit for a liquid crystal display, specifically to a drive circuit for an STN-LCD (Super Twisted Nematic Liquid Crystal Display) panel.
2. Description of the Related Art
In general, the drive circuit for the STN-LCD panel is separated into two components, i.e., a common driver and a segment driver. Each of the common driver and the segment driver outputs multi-bit drive signals to corresponding data lines (row lines or column lines), has four output transistors per bit, and outputs one of four drive voltages V1, V2, V3 and V4 by turning on one of the four output transistors while turning off the other output transistors. A liquid crystal capacitor is formed at each of intersections of the row lines and the column lines. A dot matrix liquid crystal display is performed by applying the drive voltages across the liquid crystal capacitor.
FIG. 4A is a circuit diagram of an output control circuit for one bit of the common driver. The output control circuit of the common driver has a first output transistor TR1, to a source of which the first drive voltage V1 is applied, a second output transistor TR2, to a source of which the second drive voltage V2 is applied, a third output transistor TR3, to a source of which the third drive voltage V3 is applied and a fourth output transistor TR4, to a source of which the fourth drive voltage V4 is applied. Drains of the four output transistors TR1-TR4 are connected together to an output terminal P. The first and third output transistors TR1 and TR3 are P-channel type MOS transistors, while the second and fourth output transistors TR2 and TR4 are N-channel type MOS transistors.
A gate voltage of the first output transistor TR1 is controlled by an output of a first NAND circuit 50, a gate voltage of the third output transistor TR3 is controlled by an output of a second NAND circuit 51, a gate voltage of the fourth output transistor TR4 is controlled by an output of a first NOR circuit 52 and a gate voltage of the second output transistor TR2 is controlled by an output of a second NOR circuit 53.
A dot signal DA, that is a display signal, and a reverse field signal DFB, that is a reverse of a field signal DF, are inputted to the first NAND circuit 50, while a reverse dot signal DAB, that is a reverse of the dot signal DA, and the field signal DF are inputted to the second NAND circuit 51. The dot signal DA and the field signal DF are inputted to the first NOR circuit 52, while the reverse dot signal DAB and the reverse field signal DFB are inputted to the second NOR circuit 53.
The segment driver also has an output control circuit of the same structure as the common driver. However, the reverse field signal DFB that is inputted to the output control circuit of the common driver is replaced with the field signal DF in the output control circuit of the segment driver, as shown in FIG. 4B. A truth table of the output control circuits of the common driver and the segment driver is shown in Table 2.
TABLE 2COMMON DRIVERSEGMENT DRIVERTR1TR2TR3TR4TR1TR2TR3TR4DADF    OUTPUT    OUTPUTLLHLHHV4HLHHV4LHHLLLV3HLLLV3HLLLHLV1HHHLV2HHHHHLV2LLHLV1
Further description on the technologies described above may be found in Japanese Patent Application Publication No. H11-510622, for example.
In the conventional liquid crystal display drive circuit, however, the number of transistors in the output control circuit is as many as 16, since on/off control of the output transistors are made by two NAND circuits (the first and second NAND circuits 50 and 51) and two NOR circuits (the first and second NOR circuits 52 and 53). It has caused a problem of an increased die size of an LSI that includes the drive circuit. The increase in the number of transistors has a large influence over the die size, especially because the drive voltages as high as 30V to 40V require using high withstand voltage transistors that consume large die area in designing not only the output transistors but also transistors forming the NAND circuits and the NOR circuits.
Also, a through current and a charge/discharge current in the NAND circuit, NOR circuit and output transistors are significantly increased during transition (from low to high, or from high to low) of the dot signal DA and the field signal DF, leading to an increased power consumption and fluctuations in the drive voltages.